This invention relates to code generators, particularly but not exclusively to code generators for use within a Code Division Multiple Access (CDMA) communication system.
CDMA systems are well known. See, generally, CDMA Cellular Mobile Communications and Network Security, Dr. Man Young Rhee, Prentice Hall 1998, ISBN 0-13-598418-1, and standard TIA/EIA/IS-95, hereinafter xe2x80x9cIS-95xe2x80x9d.
In CDMA systems, information bits transmitted from a mobile station to a base station may undergo convolutional encoding, symbol repetition, and block interleaving, the result of which is a bit stream comprising what are known as code symbols. As shown in FIG. 1, the code symbols are subsequently modulated into xe2x80x9cWalsh chipsxe2x80x9d and xe2x80x9cspreadxe2x80x9d into Pseudo-Noise (PN) chips by sequential bits of what is known in the CDMA art as the xe2x80x9clong codexe2x80x9d (LC). The PN chips are then Offset Quadrature Phase-Shift Keying (OQPSK) modulated into two channels, known as the I channel and the Q channel, the latter being delayed by one-half a PN chip duration. Spreading to the two channels is accomplished by adding the PN chip stream in modulo-2 arithmetic to sequential bits of two different pseudo-noise binary sequences known as PNI, and PNQ respectively. The PN chips are then converted from baseband to a radio transmission frequency for xe2x80x9cair linkxe2x80x9d (radio transmission) to the base station.
When the base station demodulates the signal, it converts back to baseband and undoes the aforementioned OQPSK modulation, long-code spreading, and Walsh modulation. To this end, counterparts of the mobile station""s Walsh functions, long code generator, PNI generator, and PNQ generator can exist in the base station in order to produce xe2x80x9clocal replicasxe2x80x9d of the codes used to spread and modulate the transmitted data. However, at the inception of transmission from the mobile station, the base station""s generators are generally not synchronized with the received signal because of, among other things, delays occurring in transmission. Also, the mobile station may introduce delay for purposes of collision avoidance. It is thus necessary for the base station to determine the amount of transmission delay in order to effect synchronization. This is done by an apparatus generally known as a xe2x80x9csearcherxe2x80x9d. It can generally be assumed that the delay will be no greater than a particular amount, known as the xe2x80x9cuncertainty regionxe2x80x9d.
Conventional searchers generally operate on a trial and error basis, trying, with use of correlator circuits, varying amounts of delay against the incoming received signal until meaningful results are obtained.
A xe2x80x9cone-branchxe2x80x9d search scheme attempts correlation against live, incoming inputs using only one correlator. Such a scheme is quite slow and cannot meet strict requirements for CDMA systems (as set forth in the IS-95 standard, for example).
A xe2x80x9cmulti-branchxe2x80x9d scheme using live input data (essentially, a plurality of one-branch searchers, each trying a different amount of delay) are commensurately faster than one-branch schemes, but in many cases still fall short of meeting strict standards, such as those for CDMA systems.
A xe2x80x9ctotal parallelxe2x80x9d search strategy optimizes searching according to the maximum-likelihood criterion. Such schemes are much faster than xe2x80x9cone-branchxe2x80x9d schemes and meet the strict requirements for CDMA systems. However, this is obtained at the expense of much greater complexity and expense.
A system of parallel correlators can also be implemented on a limited basis with the complete coverage of the required search region being accomplished with use of multiple passes of multiple correlators.
One key problem with any parallel correlation strategy, whether total or limited, though is the number of code generators required. In normal correlation schemes, there is a single code generator for every correlator. In parallel correlation setups, this adds a considerable amount of complexity to an already complex implementation. As well, this requires considerable amounts of additional gates, signalling, and access ports within the overall circuit. Hence, a single enhanced code generator is required to be implemented with parallel correlators that will allow more efficient use of available resources.
It is an object of the present invention to overcome the disadvantages of the prior art and, in particular, to provide a system and method by which parallel correlators can be implemented more efficiently.
According to a first aspect, the present invention provides a code generation apparatus arranged to be coupled to a plurality of correlation devices that are each input with a first sequence of data bits, the code generation apparatus comprising a code generator, a first shift register that comprises at least one individual register, and a state buffer; wherein the code generator generates a second sequence of data bits that is output to the first shift register and the first shift register generates at least one shifted second sequence of data bits; wherein the code generation apparatus is arranged such that each of the correlation devices is input with at least one of the second sequence of data bits and the shifted second sequence of data bits; and wherein the state buffer stores, after a predetermined number of shifts in the first shift register, storage information from at least the code generator; and outputs the storage information to at least the code generator at a predetermined restore time.
According to a second aspect, the present invention provides a correlation apparatus incorporating the code generation apparatus according to the first aspect, and further comprising a plurality of correlation devices, the correlation apparatus being input with a first sequence of data bits; wherein the correlation devices are each input with the first sequence of data bits and at least one of the second sequence of data bits and the shifted second sequence of data bits.
According to a third aspect, the present invention provides in a code generation apparatus arranged to be coupled to a plurality of correlation devices that are each input with a first sequence of data bits, a method of generating a second sequence of data bits for inputting to each of the correlation devices, the method comprising the steps of: initializing a code generator; generating a second sequence of data bits with use of the code generator; shifting the second sequence of data bits in order to generate at least one shifted second sequence of data bits with use of a first shift register; outputting at least one of the second sequence of data bits and the shifted second sequence of data bits to each of the correlation devices; after shifting the second sequence of data bits a predetermined number of shifts, saving storage information from at least the code generator; and outputting the storage information to at least the code generator at a predetermined restore time.